Digital Circuit Design Engineer

Apple

United States1w ago

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Key details

Location
United States
Work style
Onsite
Level
Mid level
Function
Hardware, mechanical & civil engineering
Focus area
other
Posted
1w ago

Skills

cad

About the role

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Design and implement custom digital circuits for SRAM design. Work with an extraordinary logic/architecture team to formulate design specifications. Define architecture/topologies optimizing for power, timing, area and yield. Perform schematic capturing, simulations/analysis, and margin verifications. Responsible for functional equivalency and DFT modeling. Work with layout team to create optimal GDS. Verify extracted GDS meets design specifications. Responsible for backend verification of layout, including IR/Electromechanical analysis. Write RTL, validating use-cases, verifying against design schematics. Support post-silicon effort to enable productization. 40 hours/week.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field.

Experience and/or education must include:

Utilizing CAD tools including Cadence Virtuoso, Spice, Layout tools, Skill language, Model Sim, Digital P&R, compilers, or simulators for design entry and analysis.
Debugging simulation failures and chip simulations on CAD software for logical and timing verification.
Utilizing knowledge of device physics and transistor for circuit optimization.
SRAM design skills to build and evaluate memory circuits.
Analyzing circuits and SPICE simulation to ensure robust operation.
Utilizing waveform viewers including SpiceExplorer or WaveView to verify circuit logic and timing.
Static Timing Analysis of an SRAM design, using NanoTime, PrimeTime or similar for static timing verification.

Preferred Qualifications

N/A

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