FE Engineer

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Description

APPLE INC has the following available in Austin, Texas. Execute development, assessment and refinement of RTL design to target power, performance, area and timing goals. Support testbench development and simulation for functional and performance verification. Explore high performance strategies and validate that RTL design meets targeted performance. Work with multi-functional engineering team to implement and validate physical design. 40 hours/week.

Minimum Qualifications

Bachelor's Degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field.

Experience and/or education must include:

Utilizing verilog to write RTL for core IPs
Performing RTL design with complex FSMs, and power savings features
Using cache coherency protocols and interfaces
Using advanced hardware prefetching techniques and algorithms
Utilizing debugging tools (e.g. Verdi), and architecture models for day-to-day maintenance of RTL code
Performing high-level micro-architecture, including designing new features for improving performance, power and timing of the chip
Analyzing timing paths using industry standard tools, and understanding of gate-level design.
Using LEC/LEQ tools and doing ECOs
Low power design concepts and implementation, including clock gating, power gating, bus gating, and reducing gate paths.

Preferred Qualifications

N/A