FE Engineer

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Description

APPLE INC has the following available in Austin, Texas. Work with architecture team to define the design microarchitecture hierarchy and interfaces and develop microarchitecture spec. Refine the spec with reviews with other teams. Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Own all aspects of RTL development design. Work and collaborate with other designers in the group to deliver results. Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block. Work with front-end synthesis/STA teams to ensure timing for the block is met. Work with power/performance and functional verification team to ensure high quality of the block. Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering or a related field and
Experience and/or education must include:
2 years of experience in the job offered or related occupation.
Translating SoC architecture requirements into microarchitecture specifications describing the functionality of the blocks within the subsystem being designed.
Coding in Verilog/System Verilog to design subsystems within the System on Chip to meet power/performance and area targets
Utilizing programming and/or scripting languages such as C++/Python/Perl to automate design development
Defining verification requirements for the subsystems designed such that verification test-cases can be written to ensure correctness of the design
Implementing industry standard SoC interconnect protocols such as AHB/AXI, CPU architecture (ARM/RISCV) and peripherals used in SoC development
Utilizing source code management tools such as Perforce/GitHub
Understanding and editing gate level netlists in order to make logical transformations to fix functional bugs in the design
Analyzing timing reports and translating this information into RTL logic changes in order to fix timing issues within the design
Analyzing static and dynamic power consumption within the design and making design optimizations to minimize power consumption within the subsystem.

Preferred Qualifications

N/A